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- 23:32, 15 July 2017 diff hist +80 SceExcpmgr →SMC calls
- 23:24, 15 July 2017 diff hist +192 SceExcpmgr →SMC calls
- 23:20, 15 July 2017 diff hist +3 Pervasive →Devices
- 22:43, 15 July 2017 diff hist +3 ScePower →scePowerSetGpuClockFrequency
- 22:42, 15 July 2017 diff hist +22 ScePower →scePowerSetGpuClockFrequency
- 17:51, 15 July 2017 diff hist +130 SceExcpmgr →SMC calls
- 17:49, 15 July 2017 diff hist +83 SceExcpmgr →SMC calls
- 16:51, 15 July 2017 diff hist +137 SceExcpmgr →SMC calls
- 16:49, 15 July 2017 diff hist +179 SceSysmem →SceCpuForKernel
- 15:51, 15 July 2017 diff hist +283 SceExcpmgr →SMC calls
- 13:22, 15 July 2017 diff hist +8 SceExcpmgr →SMC calls
- 13:21, 15 July 2017 diff hist +37 SceExcpmgr →SMC calls
- 08:51, 15 July 2017 diff hist +34 SceKernelIntrMgr →Setting up interrupt
- 08:47, 15 July 2017 diff hist +230 SceKernelIntrMgr →Setting up interrupt
- 22:39, 14 July 2017 diff hist +26 Physical Memory
- 12:33, 14 July 2017 diff hist +230 SceExcpmgr →SMC
- 22:29, 13 July 2017 diff hist +172 Caches →PL310 L2 Cache
- 22:25, 13 July 2017 diff hist +407 N Caches Created page with "= PL310 L2 Cache = The Vita uses the [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246f/index.html PL310 r3p1-50rel0] L2 cache (Cache ID Register = 0x410000..."
- 21:59, 13 July 2017 diff hist +45 Main Processor →PL310 L2 Cache
- 15:45, 12 July 2017 diff hist +27 SceSysmem →pOpt->attr bitmask
- 13:03, 12 July 2017 diff hist +2 SceSysmem →SceSysmemForKernel
- 13:01, 12 July 2017 diff hist +332 SceSysmem →sceKernelAllocMemBlockForKernel
- 11:12, 12 July 2017 diff hist +18 Pervasive →Misc
- 11:11, 12 July 2017 diff hist +245 Pervasive
- 08:35, 12 July 2017 diff hist +40 SceSyscon →Callbacks
- 23:15, 11 July 2017 diff hist +44 SceKernelIntrMgr →Registered Subinterrupts
- 22:29, 11 July 2017 diff hist +20 SceSyscon →Callbacks
- 22:09, 11 July 2017 diff hist +14 SceSyscon →Reset device
- 22:06, 11 July 2017 diff hist +22 SceSyscon →Reset device
- 21:46, 11 July 2017 diff hist +64 SceSyscon →Reset device
- 21:38, 11 July 2017 diff hist +22 SceSyscon →Reset device
- 21:29, 11 July 2017 diff hist +102 ScePower →ScePowerForDriver
- 16:58, 11 July 2017 diff hist +1,080 SceLowio →ScePervasiveForDriver
- 23:51, 10 July 2017 diff hist +22 I2C Registers →Registers
- 22:49, 10 July 2017 diff hist +7 I2C Registers →Registers
- 22:48, 10 July 2017 diff hist +24 I2C Registers →Registers
- 12:33, 10 July 2017 diff hist +24 UART Console →UART Initialization
- 12:29, 10 July 2017 diff hist +320 UART Console
- 12:26, 10 July 2017 diff hist +24 UART Console →PlayStation TV UART0 location
- 12:25, 10 July 2017 diff hist +29 N File:Pstv uart0.png PlayStation TV UART0 location
- 12:22, 10 July 2017 diff hist +23 Template:Devices
- 12:20, 10 July 2017 diff hist +62 UART Console
- 12:19, 10 July 2017 diff hist +6 SceLowio →ScePervasiveForDriver
- 12:18, 10 July 2017 diff hist +33 N UART Console Created page with "The UART0 is a debugging console."
- 12:17, 10 July 2017 diff hist +8 SceLowio →ScePervasiveForDriver_A7CE7DCC
- 12:13, 10 July 2017 diff hist +10 Pervasive →Devices
- 22:37, 8 July 2017 diff hist +12 I2C Registers →I2C Devices
- 22:02, 8 July 2017 diff hist +40 I2C Registers →I2C Devices
- 21:55, 8 July 2017 diff hist +28 I2C Registers →I2C Devices
- 21:51, 8 July 2017 diff hist +28 I2C Registers →I2C Devices